On Mon, Jan 31, 2022 at 9:05 PM Philipp Tomsich
<philipp.toms...@vrull.eu> wrote:
>
> The Zb[abcs] support code still uses the RISCV_CPU macros to access
> the configuration information (i.e., check whether an extension is
> available/enabled). Now that we provide this information directly
> from DisasContext, we can access this directly via the cfg_ptr field.
>
> Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
> Suggested-by: Richard Henderson <richard.hender...@linaro.org>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
> into DisasContext) instead of going throuhg RISCV_CPU
>
> target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 810431a1d6..f9bd3b7ec4 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -19,25 +19,25 @@
> */
>
> #define REQUIRE_ZBA(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
> + if (ctx->cfg_ptr->ext_zba) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBB(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
> + if (ctx->cfg_ptr->ext_zbb) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBC(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
> + if (ctx->cfg_ptr->ext_zbc) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBS(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
> + if (ctx->cfg_ptr->ext_zbs) { \
> return false; \
> } \
> } while (0)
> --
> 2.33.1
>
>
