On 1/25/22 12:29, Warner Losh wrote:
+ case EXCP_NOCP:
+ case EXCP_INVSTATE:
+ /*
+ * See arm/arm/undefined.c undefinedinstruction();
+ *
+ * A number of details aren't emulated (they likely don't matter):
+ * o Misaligned PC generates ILL_ILLADR
As I mentioned, misaligned pc will not come here for qemu.
In the Arm ARM, see aarch32/functions/registers/BXWritePC:
// For branches to an unaligned PC counter in A32 state, the processor takes
the branch
// and does one of:
// * Forces the address to be aligned
// * Leaves the PC unaligned, meaning the target generates a PC Alignment fault.
The hardware will either refuse to allow bit 1 to be set when bit 0 is clear, OR it will
generate a PREFETCH_DATA_ABORT for Alignment.
QEMU will do the latter.
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
