Jonathan Cameron <jonathan.came...@huawei.com> writes:
> From: Ben Widawsky <ben.widaw...@intel.com> > > A CXL component is a hardware entity that implements CXL component > registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 > general types. > 1. Host Bridge > 2. Ports (root, upstream, downstream) > 3. Devices (memory, other) > > A CXL component can be conceptually thought of as a PCIe device with > extra functionality when enumerated and enabled. For this reason, CXL > does here, and will continue to add on to existing PCI code paths. > > Host bridges will typically need to be handled specially and so they can > implement this newly introduced interface or not. All other components > should implement this interface. Implementing this interface allows the > core PCI code to treat these devices as special where appropriate. > > Signed-off-by: Ben Widawsky <ben.widaw...@intel.com> > Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com> Reviewed-by: Alex Bennée <alex.ben...@linaro.org> -- Alex Bennée
