The RISC-V Debug Support specification suggests debuggers provide
"virtual debug registers" to show state not directly visible in the ISA,
and defines one such register, `priv', which encodes the processor's
current operating mode in the two least significant bits.
GDB represents virtual debug registers in the `org.gnu.gdb.riscv.virtual'
feature of RISC-V target descriptions.
This patch adds the `v' (hypervisor virtualization mode) bit
to `priv' as specified by section 4.9.1 of version 1.0 of the
RISC-V Debug Support specification.
Signed-off-by: Konrad Schwarz <konrad.schw...@siemens.com>
---
gdb-xml/riscv-32bit-virtual.xml | 30 ++++++++++++++++++++++++++++--
gdb-xml/riscv-64bit-virtual.xml | 30 ++++++++++++++++++++++++++++--
target/riscv/gdbstub.c | 5 ++++-
3 files changed, 60 insertions(+), 5 deletions(-)
diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml
index 905f1c555d..7dad42cd67 100644
--- a/gdb-xml/riscv-32bit-virtual.xml
+++ b/gdb-xml/riscv-32bit-virtual.xml
@@ -5,7 +5,33 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
+<!-- Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com -->
+
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.riscv.virtual">
- <reg name="priv" bitsize="32"/>
+
+<feature name="org.gnu.gdb.riscv.virtual" >
+
+<enum id="priv-current_priv-type" size="4" >
+ <evalue name="user" value="0" />
+ <evalue name="supervisor" value="1" />
+ <evalue name="machine" value="3" />
+</enum>
+
+
+<flags id="priv-fields" size="4" >
+ <field name="current_priv" start="0" end="1"
+ type="priv-current_priv-type" />
+ <field name="v" start="2" end="2" />
+</flags>
+
+
+<reg name="priv"
+ bitsize="32"
+ regnum="69"
+ save-restore="no"
+ type="priv-fields"
+ group="gdb-virtual"
+/>
+
+
</feature>
diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml
index 62d86c237b..02c234670d 100644
--- a/gdb-xml/riscv-64bit-virtual.xml
+++ b/gdb-xml/riscv-64bit-virtual.xml
@@ -5,7 +5,33 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
+<!-- Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com -->
+
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-<feature name="org.gnu.gdb.riscv.virtual">
- <reg name="priv" bitsize="64"/>
+
+<feature name="org.gnu.gdb.riscv.virtual" >
+
+<enum id="priv-current_priv-type" size="8" >
+ <evalue name="user" value="0" />
+ <evalue name="supervisor" value="1" />
+ <evalue name="machine" value="3" />
+</enum>
+
+
+<flags id="priv-fields" size="8" >
+ <field name="current_priv" start="0" end="1"
+ type="priv-current_priv-type" />
+ <field name="v" start="2" end="2" />
+</flags>
+
+
+<reg name="priv"
+ bitsize="64"
+ regnum="69"
+ save-restore="no"
+ type="priv-fields"
+ group="gdb-virtual"
+/>
+
+
</feature>
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 9c3f68eeaf..b3fa9f864e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -136,7 +136,10 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs,
GByteArray *buf, int n)
#ifdef CONFIG_USER_ONLY
return gdb_get_regl(buf, 0);
#else
- return gdb_get_regl(buf, cs->priv);
+ RISCVCPU *const cpu = RISCV_CPU(cs);
+ CPURISCVState *const env = &cpu->env;
+ return gdb_get_regl(buf, riscv_cpu_virt_enabled(env) << 2 | cs->priv);
+ /* per RISCV Debug Spec 1.0, 4.9.1 */
#endif
}
return 0;
--
Konrad Schwarz
