On Sat, Dec 11, 2021 at 2:34 PM Anup Patel <anup.pa...@wdc.com> wrote:
>
> The AIA specification introduces new [m|s|vs]topi CSRs for
> reporting pending local IRQ number and associated IRQ priority.
>
> Signed-off-by: Anup Patel <anup.pa...@wdc.com>
> ---
> target/riscv/csr.c | 155 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 155 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b3edc1043..6f613d182d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -189,6 +189,15 @@ static int smode32(CPURISCVState *env, int csrno)
> return smode(env, csrno);
> }
>
> +static int aia_smode(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return smode(env, csrno);
> +}
> +
> static int aia_smode32(CPURISCVState *env, int csrno)
> {
> if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> @@ -833,6 +842,28 @@ static RISCVException rmw_mieh(CPURISCVState *env, int
> csrno,
> return ret;
> }
>
> +static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + int irq;
> + uint8_t iprio;
> +
> + irq = riscv_cpu_mirq_pending(env);
> + if (irq <= 0 || irq > 63) {
> + *val = 0;
> + } else {
> + iprio = env->miprio[irq];
> + if (!iprio) {
> + if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
> + iprio = IPRIO_MMAXIPRIO;
> + }
> + }
> + *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
> + *val |= iprio;
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mtvec(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -1362,6 +1393,121 @@ static RISCVException write_satp(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + int irq, ret;
> + target_ulong topei;
> + uint64_t vseip, vsgein;
> + uint32_t iid, iprio, hviid, hviprio, gein;
> +#define VSTOPI_NUM_SRCS 5
This should be defined at the top of the file.
Alistair
