On Mon, Nov 29, 2021 at 12:08 AM Frédéric Pétrot
<frederic.pet...@univ-grenoble-alpes.fr> wrote:
>
> This patch adds the support of the '-cpu rv128' option to
> qemu-system-riscv64 so that we can indicate that we want to run rv128
> executables.
> Still, there is no support for 128-bit insns at that stage so qemu fails
> miserably (as expected) if launched with this option.
>
> Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> include/disas/dis-asm.h | 1 +
> target/riscv/cpu.h | 1 +
> disas/riscv.c | 5 +++++
> target/riscv/cpu.c | 20 ++++++++++++++++++++
> target/riscv/gdbstub.c | 5 +++++
> 5 files changed, 32 insertions(+)
>
> diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
> index 08e1beec85..102a1e7f50 100644
> --- a/include/disas/dis-asm.h
> +++ b/include/disas/dis-asm.h
> @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*);
> int print_insn_xtensa (bfd_vma, disassemble_info*);
> int print_insn_riscv32 (bfd_vma, disassemble_info*);
> int print_insn_riscv64 (bfd_vma, disassemble_info*);
> +int print_insn_riscv128 (bfd_vma, disassemble_info*);
> int print_insn_rx(bfd_vma, disassemble_info *);
> int print_insn_hexagon(bfd_vma, disassemble_info *);
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 53a295efb7..cbd4daa6d9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -38,6 +38,7 @@
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 793ad14c27..03c8dc9961 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3090,3 +3090,8 @@ int print_insn_riscv64(bfd_vma memaddr, struct
> disassemble_info *info)
> {
> return print_insn_riscv(memaddr, info, rv64);
> }
> +
> +int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
> +{
> + return print_insn_riscv(memaddr, info, rv128);
> +}
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 364140f5ff..7f5370f2b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -178,6 +178,19 @@ static void rv64_sifive_e_cpu_init(Object *obj)
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
> +
> +static void rv128_base_cpu_init(Object *obj)
> +{
> + if (qemu_tcg_mttcg_enabled()) {
> + /* Missing 128-bit aligned atomics */
> + error_report("128-bit RISC-V currently does not work with Multi "
> + "Threaded TCG. Please use: -accel tcg,thread=single");
> + exit(EXIT_FAILURE);
> + }
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + /* We set this in the realise function */
> + set_misa(env, MXL_RV128, 0);
> +}
> #else
> static void rv32_base_cpu_init(Object *obj)
> {
> @@ -402,6 +415,9 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> disassemble_info *info)
> case MXL_RV64:
> info->print_insn = print_insn_riscv64;
> break;
> + case MXL_RV128:
> + info->print_insn = print_insn_riscv128;
> + break;
> default:
> g_assert_not_reached();
> }
> @@ -464,6 +480,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> #ifdef TARGET_RISCV64
> case MXL_RV64:
> break;
> + case MXL_RV128:
> + break;
> #endif
> case MXL_RV32:
> break;
> @@ -670,6 +688,7 @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
> case MXL_RV32:
> return g_strdup("riscv:rv32");
> case MXL_RV64:
> + case MXL_RV128:
> return g_strdup("riscv:rv64");
> default:
> g_assert_not_reached();
> @@ -822,6 +841,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> #endif
> };
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 23429179e2..2fbdcc5879 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -164,6 +164,11 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
> base_reg)
> int bitsize = 16 << env->misa_mxl_max;
> int i;
>
> + /* Until gdb knows about 128-bit registers */
> + if (bitsize > 64) {
> + bitsize = 64;
> + }
> +
> g_string_printf(s, "<?xml version=\"1.0\"?>");
> g_string_append_printf(s, "<!DOCTYPE feature SYSTEM
> \"gdb-target.dtd\">");
> g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
> --
> 2.34.0
>
>
