On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and suggestions.
v6:
- support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit
executables (no more qemu-system-riscv128)
- remove useless (and buggy) big-endian support in lq/sq
It seems like you haven't tested this with linux-user?
There are build problems:
In file included from /home/rth/qemu/qemu/include/semihosting/console.h:12,
from ../qemu/linux-user/semihost.c:14:
../qemu/target/riscv/cpu.h:485:33: error: unknown type name ‘Int128’
485 | Int128 *ret_value,
| ^~~~~~
../qemu/target/riscv/cpu.h:486:33: error: unknown type name ‘Int128’
486 | Int128 new_value, Int128 write_mask);
| ^~~~~~
../qemu/target/riscv/cpu.h:486:51: error: unknown type name ‘Int128’
486 | Int128 new_value, Int128 write_mask);
| ^~~~~~
../qemu/target/riscv/cpu.h:489:48: error: unknown type name ‘Int128’
489 | Int128 *ret_value);
| ^~~~~~
../qemu/target/riscv/cpu.h:491:46: error: unknown type name ‘Int128’
491 | Int128 new_value);
| ^~~~~~
../qemu/target/riscv/cpu.h:499:5: error: unknown type name
‘riscv_csr_read128_fn’
499 | riscv_csr_read128_fn read128;
| ^~~~~~~~~~~~~~~~~~~~
../qemu/target/riscv/cpu.h:500:5: error: unknown type name
‘riscv_csr_write128_fn’
500 | riscv_csr_write128_fn write128;
| ^~~~~~~~~~~~~~~~~~~~~
ninja: build stopped: subcommand failed.
r~
