Re: [PATCH v5 04/22] target/riscv: Create xl field in env

[Richard Henderson]

On 11/25/21 8:39 AM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
---
  target/riscv/cpu.c        | 1 +
  target/riscv/cpu.h        | 3 +++
  target/riscv/cpu_helper.c | 3 ++-
  target/riscv/csr.c        | 2 ++
  target/riscv/machine.c    | 5 +++--
  5 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..5c757ce33a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -377,6 +377,7 @@ static void riscv_cpu_reset(DeviceState *dev)
      /* mmte is supposed to have pm.current hardwired to 1 */
      env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
  #endif
+    env->xl = riscv_cpu_mxl(env);
      cs->exception_index = RISCV_EXCP_NONE;
      env->load_res = -1;
      set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0760c0af93..412339dbad 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -138,6 +138,7 @@ struct CPURISCVState {
      uint32_t misa_mxl_max;  /* max mxl for this cpu */
      uint32_t misa_ext;      /* current extensions */
      uint32_t misa_ext_mask; /* max ext for this cpu */
+    uint32_t xl;            /* current xlen */
  
      uint32_t features;
  
@@ -420,6 +421,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
  }
  #endif
  
+RISCVMXL cpu_get_xl(CPURISCVState *env);

Probably this name should be a define/inline function, just like riscv_cpu_mxl.  The 
proper function should probably be renamed cpu_recompute_xl, or something.

  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
-    .version_id = 3,
-    .minimum_version_id = 3,
+    .version_id = 4,
+    .minimum_version_id = 4,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -183,6 +183,7 @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINT32(env.misa_ext, RISCVCPU),
          VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
          VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
+        VMSTATE_UINT32(env.xl, RISCVCPU),

Do not save this.  We prefer to only save architectural state (which is of course 
required), and recompute anything else (which is qemu internal) from that in the post_load 
hook.  This allows qemu internals to change without breaking compatibility.


r~