On Tue, Nov 16, 2021 at 6:11 PM liweiwei <liwei...@iscas.ac.cn> wrote:
>
> Signed-off-by: liweiwei <liwei...@iscas.ac.cn>
> Signed-off-by: wangjunqiang <wangjunqi...@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 23 +++++++++++++++++++++++
> target/riscv/cpu.h | 13 +++++++++++++
> 2 files changed, 36 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f812998123..a5ec182a86 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -491,6 +491,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> cpu->cfg.ext_d = true;
> }
>
> + if (cpu->cfg.ext_zk) {
> + cpu->cfg.ext_zkn = true;
> + cpu->cfg.ext_zkr = true;
> + cpu->cfg.ext_zkt = true;
> + }
> +
> + if (cpu->cfg.ext_zkn) {
> + cpu->cfg.ext_zbkb = true;
> + cpu->cfg.ext_zbkc = true;
> + cpu->cfg.ext_zbkx = true;
> + cpu->cfg.ext_zkne = true;
> + cpu->cfg.ext_zknd = true;
> + cpu->cfg.ext_zknh = true;
> + }
> +
> + if (cpu->cfg.ext_zks) {
> + cpu->cfg.ext_zbkb = true;
> + cpu->cfg.ext_zbkc = true;
> + cpu->cfg.ext_zbkx = true;
> + cpu->cfg.ext_zksed = true;
> + cpu->cfg.ext_zksh = true;
> + }
> +
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_i) {
> ext |= RVI;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0760c0af93..74e8be4847 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -308,7 +308,20 @@ struct RISCVCPU {
> bool ext_zba;
> bool ext_zbb;
> bool ext_zbc;
> + bool ext_zbkb;
> + bool ext_zbkc;
> + bool ext_zbkx;
> bool ext_zbs;
> + bool ext_zk;
> + bool ext_zkn;
> + bool ext_zknd;
> + bool ext_zkne;
> + bool ext_zknh;
> + bool ext_zkr;
> + bool ext_zks;
> + bool ext_zksed;
> + bool ext_zksh;
> + bool ext_zkt;
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> --
> 2.17.1
>
>
