On Fri, Nov 12, 2021 at 2:03 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> Replace the array of pm_mask/pm_base with scalar variables.
> Remove the cached array value in DisasContext.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 32 ++++++++------------------------
> 1 file changed, 8 insertions(+), 24 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a6a73ced9e..6cb74c6355 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -37,8 +37,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> /* globals for PM CSRs */
> -static TCGv pm_mask[4];
> -static TCGv pm_base[4];
> +static TCGv pm_mask;
> +static TCGv pm_base;
>
> #include "exec/gen-icount.h"
>
> @@ -88,8 +88,6 @@ typedef struct DisasContext {
> TCGv temp[4];
> /* PointerMasking extension */
> bool pm_enabled;
> - TCGv pm_mask;
> - TCGv pm_base;
> } DisasContext;
>
> static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> @@ -297,8 +295,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv
> src)
> return src;
> } else {
> temp = temp_new(s);
> - tcg_gen_andc_tl(temp, src, s->pm_mask);
> - tcg_gen_or_tl(temp, temp, s->pm_base);
> + tcg_gen_andc_tl(temp, src, pm_mask);
> + tcg_gen_or_tl(temp, temp, pm_base);
> return temp;
> }
> }
> @@ -647,10 +645,6 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->ntemp = 0;
> memset(ctx->temp, 0, sizeof(ctx->temp));
> ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> - int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
> - ctx->pm_mask = pm_mask[priv];
> - ctx->pm_base = pm_base[priv];
> -
> ctx->zero = tcg_constant_tl(0);
> }
>
> @@ -763,19 +757,9 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
> "load_val");
> -#ifndef CONFIG_USER_ONLY
> /* Assign PM CSRs to tcg globals */
> - pm_mask[PRV_U] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask),
> "upmmask");
> - pm_base[PRV_U] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase),
> "upmbase");
> - pm_mask[PRV_S] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask),
> "spmmask");
> - pm_base[PRV_S] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase),
> "spmbase");
> - pm_mask[PRV_M] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask),
> "mpmmask");
> - pm_base[PRV_M] =
> - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase),
> "mpmbase");
> -#endif
> + pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState,
> cur_pmmask),
> + "pmmask");
> + pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState,
> cur_pmbase),
> + "pmbase");
> }
> --
> 2.25.1
>
>
