Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write

[Richard Henderson]

On 11/10/21 8:04 AM, LIU Zhiwei wrote:

Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
---
  target/riscv/csr.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, 
int csrno)
      int csr_priv = get_field(csrno, 0x300);
      int pm_current;

+ if (env->debugger) {

+        return false;
+    }
      /*
       * If priv lvls differ that means we're accessing csr from higher priv 
lvl,
       * so allow the access

Seems reasonable.

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~