On 10/29/21 23:02, BALATON Zoltan wrote: > The timer memory region is only accessed via aliases that are 0x1000 > bytes long, no need to have the timer region larger than that. > > Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu> > --- > hw/timer/sh_timer.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c > index 250ad41b48..a6445092e4 100644 > --- a/hw/timer/sh_timer.c > +++ b/hw/timer/sh_timer.c > @@ -350,8 +350,7 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base, int > feat, uint32_t freq, > ch2_irq0); /* ch2_irq1 not supported */ > } > > - memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, > - "timer", 0x100000000ULL); > + memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x1000);
Per the manual (R01UH0457EJ0401 Rev. 4.01 [*]) Page 317/1128, Table 12.2 "TMU Registers" the first 3 timers (implemented by the tmu012_state structure) fit in a region of 0x30 bytes. Looking at hw/timer/sh_timer.c I only see a maximum access of 0x40, where 0x1000 comes from? The P4/A7 aliases? If you have a way to test and ack, I can replace by 0x40 when applying. [*] https://www.renesas.com/us/en/document/mah/sh7751-group-sh7751r-group-users-manual-hardware?language=en&r=1055171
