On Wed, 20 Oct 2021 09:41:10 +0800
Bin Meng <bmeng...@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> While at it add check for user supplied RAM size and error out if it
> mismatches board expected value.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Igor Mammedov <imamm...@redhat.com>
>
> ---
>
> Changes in v2:
> - add RAM size check
> - assign mc->default_ram_size
>
> hw/riscv/sifive_e.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 6e95ea5896..9b206407a6 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -29,6 +29,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "hw/boards.h"
> @@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] = {
>
> static void sifive_e_machine_init(MachineState *machine)
> {
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> const MemMapEntry *memmap = sifive_e_memmap;
>
> SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
>
> + if (machine->ram_size != mc->default_ram_size) {
> + char *sz = size_to_str(mc->default_ram_size);
> + error_report("Invalid RAM size, should be %s", sz);
> + g_free(sz);
> + exit(EXIT_FAILURE);
> + }
> +
> /* Initialize SoC */
> object_initialize_child(OBJECT(machine), "soc", &s->soc,
> TYPE_RISCV_E_SOC);
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* Data Tightly Integrated Memory */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc,
> void *data)
> mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> + mc->default_ram_id = "riscv.sifive.e.ram";
> + mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>
> object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
> sifive_e_machine_set_revb);
