On Thu, Oct 21, 2021 at 9:25 AM Alistair Francis <alistai...@gmail.com> wrote:
>
> On Wed, Oct 20, 2021 at 1:13 PM <frank.ch...@sifive.com> wrote:
> >
> > From: Frank Chang <frank.ch...@sifive.com>
> >
> > Signed-off-by: Frank Chang <frank.ch...@sifive.com>
>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
>
> Alistair
>
> > ---
> > target/riscv/cpu.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 8c579dc297b..4c0e6532164 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -602,6 +602,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > + DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
> > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> > --
> > 2.25.1
> >
> >
