On Thu, Oct 14, 2021 at 6:54 AM Richard Henderson <richard.hender...@linaro.org> wrote: > > Shortly, the set of supported XL will not be just 32 and 64, > and representing that properly using the enumeration will be > imperative. > > Two places, booting and gdb, intentionally use misa_mxl_max > to emphasize the use of the reset value of misa.mxl, and not > the current cpu state. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/riscv/cpu.h | 9 ++++++++- > hw/riscv/boot.c | 2 +- > semihosting/arm-compat-semi.c | 2 +- > target/riscv/cpu.c | 24 ++++++++++++++---------- > target/riscv/cpu_helper.c | 12 ++++++------ > target/riscv/csr.c | 24 ++++++++++++------------ > target/riscv/gdbstub.c | 2 +- > target/riscv/monitor.c | 4 ++-- > 8 files changed, 45 insertions(+), 34 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e708fcc168..87248b562a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) > FIELD(TB_FLAGS, HLSX, 9, 1) > FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) > > -bool riscv_cpu_is_32bit(CPURISCVState *env); > +#ifdef CONFIG_RISCV32
Besides the typo: Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair
