On 10/2/21 9:37 AM, Philippe Mathieu-Daudé wrote:
-static inline void gen_mfc0_load64(TCGv arg, target_ulong off) -{ - tcg_gen_ld_tl(arg, cpu_env, off); - tcg_gen_ext32s_tl(arg, arg); -} - static inline void gen_mtc0_store32(TCGv arg, target_ulong off) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -5679,17 +5673,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
Oh, actually, this replacement only works for little-endian host. For big-endian host you'd need to adjust the offset by sizeof(target_ulong) - 4 r~