> -----Original Message-----
> From: Richard Henderson <richard.hender...@linaro.org>
> Sent: Friday, October 1, 2021 10:55 AM
> To: Taylor Simpson <tsimp...@quicinc.com>; qemu-devel@nongnu.org
> Cc: f4...@amsat.org; a...@rev.ng; Brian Cain <bc...@quicinc.com>
> Subject: Re: [PATCH v2] Hexagon (target/hexagon) probe the stores in a
> packet at start of commit
>
> On 9/30/21 5:16 PM, Taylor Simpson wrote:
> > + } else if (has_store_s0 && has_store_s1) {
> > + TCGv mem_idx = tcg_const_tl(ctx->mem_idx);
> > + gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
> > + tcg_temp_free(mem_idx);
> > + }
>
> So we're assuming that the s1 store happens first?
> If so, you could expand the comment above.
Yes, there's a comment in process_store_log (with a typo fixed here).
/*
* When a packet has two stores, the hardware processes
* slot 1 and then slot 0. This will be important when
* the memory accesses overlap.
*/
I'll fix the typo and expand the comment in the above code.
Also, tests/tcg/hexagon/dual_stores.c tests for this behavior.
> Otherwise, it looks good.
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Thanks!
