On 9/21/21 9:29 AM, Peter Maydell wrote:
Cortex-M CPUs with MVE should advertise this fact to gdb, using the
org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR
register. Presence of this feature also tells gdb to create
pseudo-registers Q0..Q7, so we do not need to tell gdb about them
separately.
Note that unless you have a very recent GDB that includes this fix:
http://patches-tcwg.linaro.org/patch/58133/ gdb will mis-print the
individual fields of the VPR register as zero (but showing the whole
thing as hex, eg with "print /x $vpr" will give the correct value).
NB: the gdb patches to implement this have not yet landed in
gdb upstream, so this patch is RFC status only until that
happens and the XML is finalized.
Signed-off-by: Peter Maydell<peter.mayd...@linaro.org>
---
configs/targets/aarch64-softmmu.mak | 2 +-
configs/targets/arm-linux-user.mak | 2 +-
configs/targets/arm-softmmu.mak | 2 +-
configs/targets/armeb-linux-user.mak | 2 +-
target/arm/gdbstub.c | 25 +++++++++++++++++++++++++
gdb-xml/arm-m-profile-mve.xml | 19 +++++++++++++++++++
6 files changed, 48 insertions(+), 4 deletions(-)
create mode 100644 gdb-xml/arm-m-profile-mve.xml
Looks like it'll do what's advertised.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
