On 9/13/21 7:22 AM, Peter Maydell wrote:
On Mon, 13 Sept 2021 at 15:04, Richard Henderson
<richard.hender...@linaro.org> wrote:
On 9/13/21 2:54 AM, Peter Maydell wrote:
Optimize the MVE VSHLL insns by using TCG vector ops when possible.
This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
with zero shift count".
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
The cases here that I've implemented with ANDI then shift
could also be implemented as shift-then-shift. Is one better
than another?
I would expect and + shift to be preferred over shift + shift.
OK. (I wasn't sure, because and + shift requires another insn
to assemble the immediate constant, I think.)
Yea, though Arm itself is good about not requiring one. But there's generally only one
shifter across multiple pipelines. Not that we're doing any sort of compute resource
allocation and scheduling...
r~
