This patchset uses the TCG vector ops for some MVE instructions. We can only do this when we know that none of the MVE lanes are predicated, ie when neither tail predication nor VPT predication nor ECI partial insn execution are happening.
Patch 1 adds a TB flag so we can track whether we can safely assume that the insn operates on the entire vector, and patches 2, 3, 4 use that to vectorize some simple cases (bitwise logic ops, integer add, sub, mul, min, max, abs and neg). This small initial patchset is intended as a check that the general structure for handling this makes sense; there are almost certainly other places we could improve the codegen for the non-predicated case. Richard: if you have time to scan through the MVE insns and suggest which ones would benefit from a vectorized version that would be very helpful... thanks -- PMM Peter Maydell (4): target/arm: Add TB flag for "MVE insns not predicated" target/arm: Optimize MVE logic ops target/arm: Optimize MVE arithmetic ops target/arm: Optimize MVE VNEG, VABS target/arm/cpu.h | 4 +- target/arm/translate.h | 2 + target/arm/helper.c | 23 ++++++++ target/arm/translate-m-nocp.c | 8 +++ target/arm/translate-mve.c | 102 ++++++++++++++++++++++------------ target/arm/translate-vfp.c | 3 + target/arm/translate.c | 4 ++ 7 files changed, 110 insertions(+), 36 deletions(-) -- 2.20.1
