[PATCH 2/8] target/riscv: 128-bit registers creation and access

[Frédéric Pétrot]

Addition of the upper 64 bits of the 128-bit registers, along with
the setter and getter for them and creation of the corresponding
global tcg values.

Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
---
 slirp                    |  2 +-
 target/riscv/cpu.h       |  3 +++
 target/riscv/translate.c | 30 ++++++++++++++++++++++++++++++
 3 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/slirp b/slirp
index a88d9ace23..8f43a99191 160000
--- a/slirp
+++ b/slirp
@@ -1 +1 @@
-Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0
+Subproject commit 8f43a99191afb47ca3f3c6972f6306209f367ece
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d1a73276fb..6528b4540e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -120,6 +120,9 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
     target_ulong gpr[32];
+#if defined(TARGET_RISCV128)
+    target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
+#endif
     uint64_t fpr[32]; /* assume both F and D extensions */
 
     /* vector coprocessor state. */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 713b14da8b..be9c64f3e4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -33,6 +33,9 @@
 
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+#if defined(TARGET_RISCV128)
+static TCGv cpu_gprh[32];
+#endif
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
@@ -211,6 +214,17 @@ static inline void gen_get_gpr(TCGv t, int reg_num)
     }
 }
 
+#if defined(TARGET_RISCV128)
+static inline void gen_get_gprh(TCGv t, int reg_num)
+{
+    if (reg_num == 0) {
+        tcg_gen_movi_tl(t, 0);
+    } else {
+        tcg_gen_mov_tl(t, cpu_gprh[reg_num]);
+    }
+}
+#endif
+
 /* Wrapper for setting reg values - need to check of reg is zero since
  * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
@@ -223,6 +237,15 @@ static inline void gen_set_gpr(int reg_num_dst, TCGv t)
     }
 }
 
+#if defined(TARGET_RISCV128)
+static inline void gen_set_gprh(int reg_num_dst, TCGv t)
+{
+    if (reg_num_dst != 0) {
+        tcg_gen_mov_tl(cpu_gprh[reg_num_dst], t);
+    }
+}
+#endif
+
 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 {
     TCGv rl = tcg_temp_new();
@@ -1074,10 +1097,17 @@ void riscv_translate_init(void)
     /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
     /* registers, unless you specifically block reads/writes to reg 0 */
     cpu_gpr[0] = NULL;
+#if defined(TARGET_RISCV128)
+    cpu_gprh[0] = NULL;
+#endif
 
     for (i = 1; i < 32; i++) {
         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
+#if defined(TARGET_RISCV128)
+        cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+            offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
+#endif
     }
 
     for (i = 0; i < 32; i++) {
-- 
2.33.0