This series of patches aims at adding partial 128-bit support to the riscv target, following the (unratified) RV128I specification, Chapter 7 of riscv-spec document dated 20191214. It provides support for all user integer (I) instructions and for an M extension which follows the definition of the 32 and 64-bit specifications. We also included minimal support for 128-bit csrs. Among the csrs, we selected misa, to know the mxlen in which the processor is, mtvec, mepc, mscratch and mstatus for minimal kernel development, and satp to point to the page table. We fallback on the 64-bit csrs for the others.
In the last patch, we propose a "natural" extension of the sv39 and sv48 virtual address modes using 16KB pages, that we believe suitable for 128-bit CPU workloads. There are two strong assumptions in this implementation: - the 64 upper bits of the addresses are irrelevant, be they virtual or physical, in order to use the existing address translation mechanism, - the mxlen field stays hardwired, so there is no dynamic change in register size. As no toolchain exists yet for this target, we wrote all our tests in asm using macros expanding .insn directives. We unit tested the behavior of the instructions, and wrote some simple user level performance tests: on our examples the execution speed of the 128-bit version is between 1.2 to 5 time slower than its 32 and 64-bit counterparts. Thanks to Luc Michel for his advice in building the patches (although all errors are ours.) Frédéric Pétrot (8): target/riscv: Settings for 128-bit extension support target/riscv: 128-bit registers creation and access target/riscv: Addition of 128-bit ldu, lq and sq instructions target/riscv: 128-bit arithmetic and logic instructions target/riscv: 128-bit multiply and divide target/riscv: Support of compiler's 128-bit integer types target/riscv: 128-bit support for some csrs target/riscv: Support for 128-bit satp configs/devices/riscv128-softmmu/default.mak | 16 + configs/targets/riscv128-softmmu.mak | 5 + gdb-xml/riscv-128bit-cpu.xml | 48 + gdb-xml/riscv-128bit-virtual.xml | 12 + include/hw/riscv/sifive_cpu.h | 4 + include/tcg/tcg-op.h | 1 + slirp | 2 +- target/riscv/Kconfig | 3 + target/riscv/arch_dump.c | 3 +- target/riscv/cpu-param.h | 12 +- target/riscv/cpu.c | 51 +- target/riscv/cpu.h | 61 + target/riscv/cpu_bits.h | 12 + target/riscv/cpu_helper.c | 56 +- target/riscv/csr.c | 343 ++++- target/riscv/gdbstub.c | 3 + target/riscv/helper.h | 15 + target/riscv/insn16.decode | 33 +- target/riscv/insn32.decode | 25 + target/riscv/insn_trans/trans_rvd.c.inc | 10 +- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 1209 +++++++++++++++++- target/riscv/insn_trans/trans_rvm.c.inc | 456 ++++++- target/riscv/m128_helper.c | 349 +++++ target/riscv/meson.build | 1 + target/riscv/op_helper.c | 60 + target/riscv/translate.c | 104 +- target/riscv/utils_128.h | 173 +++ tcg/tcg-op.c | 6 + 29 files changed, 2990 insertions(+), 85 deletions(-) create mode 100644 configs/devices/riscv128-softmmu/default.mak create mode 100644 configs/targets/riscv128-softmmu.mak create mode 100644 gdb-xml/riscv-128bit-cpu.xml create mode 100644 gdb-xml/riscv-128bit-virtual.xml create mode 100644 target/riscv/m128_helper.c create mode 100644 target/riscv/utils_128.h -- 2.33.0
