On 8/20/21 3:34 AM, Peter Maydell wrote:
On Wed, 18 Aug 2021 at 22:32, Richard Henderson
<richard.hender...@linaro.org> wrote:
From armv6, the architecture supports unaligned accesses.
All we need to do is perform the correct alignment check
in tcg_out_tlb_read and not use LDRD/STRD when the access
is not aligned.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
@@ -1578,27 +1576,32 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg
addrlo, TCGReg addrhi,
/*
* Check alignment, check comparators.
- * Do this in no more than 3 insns. Use MOVW for v7, if possible,
+ * Do this in 2-4 insns. Use MOVW for v7, if possible,
* to reduce the number of sequential conditional instructions.
* Almost all guests have at least 4k pages, which means that we need
* to clear at least 9 bits even for an 8-byte memory, which means it
* isn't worth checking for an immediate operand for BIC.
*/
+ /* For unaligned accesses, test the page of the last byte. */
+ t_addr = addrlo;
+ if (a_mask < s_mask) {
+ t_addr = TCG_REG_R0;
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
+ addrlo, s_mask - a_mask);
+ }
I don't understand what this comment means or why we're doing the
addition. If we know we need to check eg whether the address is 2-aligned,
why aren't we just checking whether it's 2-aligned ? Could you
expand on the explanation a bit?
We want to detect the page crossing case of a misaligned access.
We began computing the softtlb data with the address of the start access (addrlo). We
then compute the address of the last (aligned) portion of the access. For a 4-byte access
that is 1-byte aligned, we add 3 - 0 = 3, finding the last byte; for a 2-byte aligned
access we add 3 - 1 = 2; for a 4-byte aligned access we (logically) add 3 - 3 = 0.
This second quantity retains the alignment we need to test and also rolls over to the next
page iff the access does. When we compare against the comparator in the tlb, a bit set
within the alignment will cause failure as will a differing page number.
r~
