From: Gustavo Romero <grom...@linux.ibm.com> An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens.
The EBB will: - set the Global Enable (GE) bit of BESCR to 0; - set bits 0-61 of the Event-Based Branch Return Register (EBBRR) to the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but next patches will use the remaining bits. Note that we're implementing the extended rfebb mnemonic (BESCR_GE is being always set to 1). The basic rfebb instruction would accept an operand that would be used to set GE. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf CC: Gustavo Romero <gustavo.rom...@linaro.org> Signed-off-by: Gustavo Romero <grom...@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com> --- target/ppc/cpu.h | 12 ++++++++++++ target/ppc/translate.c | 21 +++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index afd9cd402b..ae431e65be 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -358,6 +358,18 @@ typedef struct ppc_v3_pate_t { #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 62356cfadf..afc254a03f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2701,6 +2701,26 @@ static void gen_darn(DisasContext *ctx) } } } + +/* rfebb */ +static void gen_rfebb(DisasContext *ctx) +{ + TCGv target = tcg_temp_new(); + TCGv bescr = tcg_temp_new(); + + gen_load_spr(target, SPR_EBBRR); + tcg_gen_mov_tl(cpu_nip, target); + + gen_load_spr(bescr, SPR_BESCR); + tcg_gen_ori_tl(bescr, bescr, BESCR_GE); + gen_store_spr(SPR_BESCR, bescr); + + ctx->base.is_jmp = DISAS_EXIT; + + tcg_temp_free(target); + tcg_temp_free(bescr); +} + #endif /*** Integer rotate ***/ @@ -7724,6 +7744,7 @@ GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(rfebb, 0x13, 0x12, 0x04, 0x03FFF001, PPC_NONE, PPC2_ISA207S), GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), #endif -- 2.31.1
