From: Gustavo Romero <grom...@linux.ibm.com>
Similar to the previous patch, write read on PowerPC PMU regs
requires extra handling than the generic write ureg functions.
This patch adds a specific write function for user PMU SPRs,
spr_write_pmu_ureg(). MMCR0 and PMC1 are being treated before
write, all other registers will be default to what is done in
spr_write_ureg(), for now.
Since spr_write_pmu_ureg() needs to have a look in SPR_POWER_MMCR0
to validate if the write is valid or not, we're adding a 'spr'
array in DisasContext that points to env->spr.
CC: Gustavo Romero <gustavo.rom...@linaro.org>
Signed-off-by: Gustavo Romero <grom...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
---
target/ppc/cpu_init.c | 26 +++++++++++++-------------
target/ppc/spr_tcg.h | 1 +
target/ppc/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 56 insertions(+), 13 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d30aa0fe1e..71062809c8 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6868,47 +6868,47 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState
*env)
static void register_book3s_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC1, "UPMC1",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC2, "UPMC2",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC3, "UPMC3",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC4, "UPMC4",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC5, "UPMC5",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_UPMC6, "UPMC6",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_USIAR, "USIAR",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
spr_register(env, SPR_POWER_USDAR, "USDAR",
- &spr_read_pmu_ureg, SPR_NOACCESS,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
&spr_read_ureg, &spr_write_ureg,
0x00000000);
}
@@ -6976,8 +6976,8 @@ static void register_power8_pmu_sup_sprs(CPUPPCState *env)
static void register_power8_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
- &spr_read_pmu_ureg, SPR_NOACCESS,
- &spr_read_pmu_ureg, &spr_write_ureg,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
+ &spr_read_pmu_ureg, &spr_write_pmu_ureg,
0x00000000);
spr_register(env, SPR_POWER_USIER, "USIER",
&spr_read_generic, SPR_NOACCESS,
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 84ecba220f..40b5de34b9 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn);
void spr_read_pmu_ureg(DisasContext *ctx, int gprn, int sprn);
+void spr_write_pmu_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d3a4d42ff8..29b0a340a9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -176,6 +176,7 @@ struct DisasContext {
bool tm_enabled;
bool gtse;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
+ target_ulong *spr; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint32_t flags;
uint64_t insns_flags;
@@ -573,6 +574,46 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
{
gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
}
+
+/* User special write access to PMU SPRs */
+void spr_write_pmu_ureg(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0, t1;
+ int effective_sprn = sprn + 0x10;
+
+ if (((ctx->spr[SPR_POWER_MMCR0] & MMCR0_PMCC) >> 18) == 0) {
+ /* Hypervisor Emulation Assistance interrupt */
+ gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ return;
+ }
+
+ switch (effective_sprn) {
+ case SPR_POWER_MMCR0:
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ /*
+ * Filter out all bits but FC, PMAO, and PMAE, according
+ * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0,
+ * fourth paragraph.
+ */
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn],
+ MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE);
+ gen_load_spr(t1, SPR_POWER_MMCR0);
+ tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE));
+ /* Keep all other bits intact */
+ tcg_gen_or_tl(t1, t1, t0);
+ gen_store_spr(effective_sprn, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ break;
+ default:
+ gen_store_spr(effective_sprn, cpu_gpr[gprn]);
+ break;
+ }
+}
+
#endif
/* SPR common to all non-embedded PowerPC */
@@ -8563,6 +8604,7 @@ static void ppc_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
uint32_t hflags = ctx->base.tb->flags;
ctx->spr_cb = env->spr_cb;
+ ctx->spr = env->spr;
ctx->pr = (hflags >> HFLAGS_PR) & 1;
ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
ctx->dr = (hflags >> HFLAGS_DR) & 1;
--
2.31.1
