On Mon, Aug 9, 2021 at 6:37 PM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> For U-mode CSRs, read-only check is also needed.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> ---
> target/riscv/csr.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9a4ed18ac5..360e4bfa33 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int
> csrno,
> RISCVException ret;
> target_ulong old_value;
> RISCVCPU *cpu = env_archcpu(env);
> + int read_only = get_field(csrno, 0xC00) == 3;
>
> /* check privileges and return -1 if check fails */
> #if !defined(CONFIG_USER_ONLY)
> int effective_priv = env->priv;
> - int read_only = get_field(csrno, 0xC00) == 3;
>
> if (riscv_has_ext(env, RVH) &&
> env->priv == PRV_S &&
> @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int
> csrno,
> effective_priv++;
> }
>
> - if ((write_mask && read_only) ||
> - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
> + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> #endif
> + if (write_mask && read_only) {
> + return -RISCV_EXCP_ILLEGAL_INST;
This should be RISCV_EXCP_ILLEGAL_INST
> + }
>
> /* ensure the CSR extension is enabled. */
> if (!cpu->cfg.ext_icsr) {
Otherwise,
Reviewed-by: Bin Meng <bmeng...@gmail.com>
