On Tue, 27 Jul 2021 at 11:48, Peter Maydell <peter.mayd...@linaro.org> wrote: > > arm pullreq for rc1. All minor bugfixes, except for the > sve-default-vector-length > patches, which are somewhere between a bugfix and a new feature. > > thanks > -- PMM > > The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a: > > Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' > into staging (2021-07-27 08:35:01 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20210727 > > for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749: > > hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * hw/arm/smmuv3: Check 31st bit to see if CD is valid > * qemu-options.hx: Fix formatting of -machine memory-backend option > * hw: aspeed_gpio: Fix memory size > * hw/arm/nseries: Display hexadecimal value with '0x' prefix > * Add sve-default-vector-length cpu property > * docs: Update path that mentions deprecated.rst > * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS > * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING > * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending > interrupts > * target/arm: Report M-profile alignment faults correctly to the guest > * target/arm: Add missing 'return's after calling v7m_exception_taken() > * target/arm: Enforce that M-profile SP low 2 bits are always zero >
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1 for any user-visible changes. -- PMM
