Re: [PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

[Bin Meng]

On Wed, Jul 14, 2021 at 3:24 PM Alistair Francis
<alistair.fran...@wdc.com> wrote:
>
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> Reviewed-by: Bin Meng <bmeng...@gmail.com>
> ---
>  target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>

Tested-by: Bin Meng <bmeng...@gmail.com>