On Wed, 7 Jul 2021 at 03:18, Shashi Mallela <shashi.mall...@linaro.org> wrote:
>
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
> Each of these commands make use of other functionalities implemented to
> get device table entry,collection table entry or interrupt translation
> table entry required for their processing.
>
> Signed-off-by: Shashi Mallela <shashi.mall...@linaro.org>
Couple of minor things below; otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
> +static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t dte,
> + uint16_t *icid, uint32_t *pIntid, MemTxResult *res)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint64_t itt_addr;
> + bool status = false;
> + IteEntry ite;
> +
> + itt_addr = (dte & GITS_DTE_ITTADDR_MASK) >> GITS_DTE_ITTADDR_SHIFT;
> + itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> +
> + memset(&ite, 0 , sizeof(ite));
"IteEntry ite = {};" will zero-initialize it without the need for a memset.
> + ite.itel = address_space_ldq_le(as, itt_addr +
> + (eventid * sizeof(uint64_t)),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + ite.iteh = address_space_ldl_le(as, itt_addr + ((eventid +
> + sizeof(uint64_t)) * sizeof(uint32_t)),
> + MEMTXATTRS_UNSPECIFIED, res);
> +
> + if (*res == MEMTX_OK) {
> + if (ite.itel & TABLE_ENTRY_VALID_MASK) {
> + if ((ite.itel >> ITE_ENTRY_INTTYPE_SHIFT) &
> + GITS_TYPE_PHYSICAL) {
> + *pIntid = (ite.itel & ITE_ENTRY_INTID_MASK) >>
> + ITE_ENTRY_INTID_SHIFT;
> + *icid = ite.iteh & ITE_ENTRY_ICID_MASK;
> + status = true;
> + }
> + }
> + }
> + }
> + return status;
> +}
> +/*
> + * This function handles the processing of following commands based on
> + * the ItsCmdType parameter passed:-
> + * 1. triggering of lpi interrupt translation via ITS INT command
> + * 2. triggering of lpi interrupt translation via gits_translater register
> + * 3. handling of ITS CLEAR command
> + * 4. handling of ITS DISCARD command
> + */
> +static MemTxResult process_its_cmd(GICv3ITSState *s, uint64_t value,
> + uint32_t offset, ItsCmdType cmd)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid, eventid;
> + MemTxResult res = MEMTX_OK;
> + bool dte_valid;
> + uint64_t dte = 0;
> + uint32_t max_eventid;
> + uint16_t icid = 0;
> + uint32_t pIntid = 0;
> + bool ite_valid = false;
> + uint64_t cte = 0;
> + bool cte_valid = false;
> + IteEntry ite;
> +
> + if (cmd == NONE) {
> + devid = offset;
> + } else {
> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> + }
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + eventid = (value & EVENTID_MASK);
> +
> + dte = get_dte(s, devid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> +
> + if (dte_valid) {
> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> +
> + ite_valid = get_ite(s, eventid, dte, &icid, &pIntid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + if (ite_valid) {
> + cte_valid = get_cte(s, icid, &cte, &res);
> + }
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + }
> +
> + if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
> + !cte_valid || (eventid > max_eventid)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid command attributes "
> + "devid %d or eventid %d or invalid dte %d or"
> + "invalid cte %d or invalid ite %d\n",
> + __func__, devid, eventid, dte_valid, cte_valid,
> + ite_valid);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + /*
> + * Current implementation only supports rdbase == procnum
> + * Hence rdbase physical address is ignored
> + */
> + if (cmd == DISCARD) {
> + memset(&ite, 0 , sizeof(ite));
Again here you could make 'ite' local to this code block and write
it "IteEntry ite = {};" instead of the memset.
> + /* remove mapping from interrupt translation table */
> + res = update_ite(s, eventid, dte, ite);
> + }
> + }
> +
> + return res;
> +}
> +
> +static MemTxResult process_mapti(GICv3ITSState *s, uint64_t value,
> + uint32_t offset, bool ignore_pInt)
> +{
> + AddressSpace *as = &s->gicv3->dma_as;
> + uint32_t devid, eventid;
> + uint32_t pIntid = 0;
> + uint32_t max_eventid, max_Intid;
> + bool dte_valid;
> + MemTxResult res = MEMTX_OK;
> + uint16_t icid = 0;
> + uint64_t dte = 0;
> + IteEntry ite;
> + uint32_t int_spurious = INTID_SPURIOUS;
> +
> + devid = ((value & DEVID_MASK) >> DEVID_SHIFT);
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + eventid = (value & EVENTID_MASK);
> +
> + if (!ignore_pInt) {
> + pIntid = ((value & pINTID_MASK) >> pINTID_SHIFT);
> + }
> +
> + offset += NUM_BYTES_IN_DW;
> + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> + MEMTXATTRS_UNSPECIFIED, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> +
> + icid = value & ICID_MASK;
> +
> + dte = get_dte(s, devid, &res);
> +
> + if (res != MEMTX_OK) {
> + return res;
> + }
> + dte_valid = dte & TABLE_ENTRY_VALID_MASK;
> +
> + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> +
> + if (!ignore_pInt) {
> + max_Intid = (1ULL << (GICD_TYPER_IDBITS + 1));
This is off by one -- the maximum int ID is
(1ULL << (GICD_TYPER_IDBITS + 1)) - 1
(if you have N bits then the largest ID value is 0b111..111,
not 0b100...000).
> + }
> +
> + if ((devid > s->dt.maxids.max_devids) || (icid >
> s->ct.maxids.max_collids)
> + || !dte_valid || (eventid > max_eventid) ||
> + (!ignore_pInt && ((pIntid < GICV3_LPI_INTID_START) ||
> + (pIntid > max_Intid)))) {
1023 is also a permitted value here (meaning "no interrupt").
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid command attributes "
> + "devid %d or icid %d or eventid %d or pIntid %d or"
> + "unmapped dte %d\n", __func__, devid, icid, eventid,
> + pIntid, dte_valid);
> + /*
> + * in this implementation, in case of error
> + * we ignore this command and move onto the next
> + * command in the queue
> + */
> + } else {
> + memset(&ite, 0 , sizeof(ite));
> + /* add ite entry to interrupt translation table */
> + ite.itel = (dte_valid & TABLE_ENTRY_VALID_MASK) |
> + (GITS_TYPE_PHYSICAL << ITE_ENTRY_INTTYPE_SHIFT);
> +
> + if (ignore_pInt) {
> + ite.itel |= (eventid << ITE_ENTRY_INTID_SHIFT);
> + } else {
> + ite.itel |= (pIntid << ITE_ENTRY_INTID_SHIFT);
> + }
> + ite.itel |= (int_spurious << ITE_ENTRY_INTSP_SHIFT);
> + ite.iteh |= icid;
If you use "=" here instead of "|=" to set ite.iteh then you've
explicitly set all the members of "ite" and you don't need the
memset at all.
> +
> + res = update_ite(s, eventid, dte, ite);
> + }
> +
> + return res;
> +}
> +
> static MemTxResult update_cte(GICv3ITSState *s, uint16_t icid, bool valid,
> uint64_t rdbase)
> {
> @@ -128,7 +461,8 @@ static MemTxResult process_mapc(GICv3ITSState *s,
> uint32_t offset)
>
> icid = value & ICID_MASK;
>
> - rdbase = (value >> R_MAPC_RDBASE_SHIFT) & RDBASE_PROCNUM_MASK;
> + rdbase = (value & R_MAPC_RDBASE_MASK) >> R_MAPC_RDBASE_SHIFT;
> + rdbase &= RDBASE_PROCNUM_MASK;
This looks like something that should have been squashed into a
previous patch.
thanks
-- PMM
