On Thu, Jun 24, 2021 at 9:14 PM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > > This patchset implements the packed extension for RISC-V on QEMU. > > You can also find this patch set on my > repo(https://github.com/romanheros/qemu.git branch:packed-upstream-v3). > > Features: > * support specification packed extension > v0.9.4(https://github.com/riscv/riscv-p-spec/) > * support basic packed extension. > * support Zpsoperand.
There is now a 0.9.5, do you have plans to support that? Alistair > > v3: > * split 32 bit vector operations. > > v2: > * remove all the TARGET_RISCV64 macro. > * use tcg_gen_vec_* to accelabrate. > * update specficication to latest v0.9.4 > * fix kmsxda32, kmsda32,kslra32,smal > > LIU Zhiwei (37): > target/riscv: implementation-defined constant parameters > target/riscv: Make the vector helper functions public > target/riscv: 16-bit Addition & Subtraction Instructions > target/riscv: 8-bit Addition & Subtraction Instruction > target/riscv: SIMD 16-bit Shift Instructions > target/riscv: SIMD 8-bit Shift Instructions > target/riscv: SIMD 16-bit Compare Instructions > target/riscv: SIMD 8-bit Compare Instructions > target/riscv: SIMD 16-bit Multiply Instructions > target/riscv: SIMD 8-bit Multiply Instructions > target/riscv: SIMD 16-bit Miscellaneous Instructions > target/riscv: SIMD 8-bit Miscellaneous Instructions > target/riscv: 8-bit Unpacking Instructions > target/riscv: 16-bit Packing Instructions > target/riscv: Signed MSW 32x32 Multiply and Add Instructions > target/riscv: Signed MSW 32x16 Multiply and Add Instructions > target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions > target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions > target/riscv: Partial-SIMD Miscellaneous Instructions > target/riscv: 8-bit Multiply with 32-bit Add Instructions > target/riscv: 64-bit Add/Subtract Instructions > target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions > target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract > Instructions > target/riscv: Non-SIMD Q15 saturation ALU Instructions > target/riscv: Non-SIMD Q31 saturation ALU Instructions > target/riscv: 32-bit Computation Instructions > target/riscv: Non-SIMD Miscellaneous Instructions > target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions > target/riscv: RV64 Only SIMD 32-bit Shift Instructions > target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions > target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions > target/riscv: RV64 Only 32-bit Multiply Instructions > target/riscv: RV64 Only 32-bit Multiply & Add Instructions > target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions > target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions > target/riscv: RV64 Only 32-bit Packing Instructions > target/riscv: configure and turn on packed extension from command line > > target/riscv/cpu.c | 34 + > target/riscv/cpu.h | 6 + > target/riscv/helper.h | 330 ++ > target/riscv/insn32.decode | 370 +++ > target/riscv/insn_trans/trans_rvp.c.inc | 1155 +++++++ > target/riscv/internals.h | 50 + > target/riscv/meson.build | 1 + > target/riscv/packed_helper.c | 3851 +++++++++++++++++++++++ > target/riscv/translate.c | 3 + > target/riscv/vector_helper.c | 82 +- > 10 files changed, 5824 insertions(+), 58 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc > create mode 100644 target/riscv/packed_helper.c > > -- > 2.17.1 > >
