On 6/28/21 7:43 AM, Peter Maydell wrote:
On Sat, 26 Jun 2021 at 07:44, Richard Henderson
<richard.hender...@linaro.org> wrote:
For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
easily provide the extension to 64-bits. Drop the special case,
previously used, where the input is already zero-extended -- the
minor code size savings is not worth the complication.
Cc: qemu-s3...@nongnu.org
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
+ case INDEX_op_bswap32_i32:
tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
break;
When we're working with i32s, is the top half of the host register
zero or garbage ?
The general case on s390x is that the top half of the host register is unmodified by insns
with 32-bit operands. This is true for LRVR.
It's also true for LRVRH, with its 16-bit operand. Which is why it's not as useful as it
could be.
r~
