SIMD 32-bit absolute value, signed or unsigned maximum, minimum.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
---
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvp.c.inc | 15 +++++++
target/riscv/packed_helper.c | 55 +++++++++++++++++++++++++
4 files changed, 82 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3b2a73db9a..d992859747 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1437,3 +1437,9 @@ DEF_HELPER_3(sll32, i64, env, i64, i64)
DEF_HELPER_3(ksll32, i64, env, i64, i64)
DEF_HELPER_3(kslra32, i64, env, i64, i64)
DEF_HELPER_3(kslra32_u, i64, env, i64, i64)
+
+DEF_HELPER_3(smin32, i64, env, i64, i64)
+DEF_HELPER_3(umin32, i64, env, i64, i64)
+DEF_HELPER_3(smax32, i64, env, i64, i64)
+DEF_HELPER_3(umax32, i64, env, i64, i64)
+DEF_HELPER_2(kabs32, tl, env, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 80150c693a..ee5f855f28 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1060,3 +1060,9 @@ ksll32 0110010 ..... ..... 010 ..... 1110111 @r
kslli32 1000010 ..... ..... 010 ..... 1110111 @sh5
kslra32 0101011 ..... ..... 010 ..... 1110111 @r
kslra32_u 0110011 ..... ..... 010 ..... 1110111 @r
+
+smin32 1001000 ..... ..... 010 ..... 1110111 @r
+umin32 1010000 ..... ..... 010 ..... 1110111 @r
+smax32 1001001 ..... ..... 010 ..... 1110111 @r
+umax32 1010001 ..... ..... 010 ..... 1110111 @r
+kabs32 1010110 10010 ..... 000 ..... 1110111 @r2
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 6cba14be84..77586e07e4 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1088,3 +1088,18 @@ GEN_RVP64_R_OOL(kslra32);
GEN_RVP64_R_OOL(sra32_u);
GEN_RVP64_R_OOL(srl32_u);
GEN_RVP64_R_OOL(kslra32_u);
+
+/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */
+GEN_RVP64_R_OOL(smin32);
+GEN_RVP64_R_OOL(umin32);
+GEN_RVP64_R_OOL(smax32);
+GEN_RVP64_R_OOL(umax32);
+
+#define GEN_RVP64_R2_OOL(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r2 *a) \
+{ \
+ REQUIRE_64BIT(s); \
+ return r2_ool(s, a, gen_helper_##NAME); \
+}
+
+GEN_RVP64_R2_OOL(kabs32);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 74d42e4c33..a808dae9d8 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3367,3 +3367,58 @@ static inline void do_kslra32_u(CPURISCVState *env, void
*vd, void *va,
}
RVPR64_64_64(kslra32_u, 1, 4);
+
+/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */
+static inline void do_smin32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR64_64_64(smin32, 1, 4);
+
+static inline void do_umin32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR64_64_64(umin32, 1, 4);
+
+static inline void do_smax32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR64_64_64(smax32, 1, 4);
+
+static inline void do_umax32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR64_64_64(umax32, 1, 4);
+
+static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+ int32_t *d = vd, *a = va;
+
+ if (a[i] == INT32_MIN) {
+ d[i] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[i] = abs(a[i]);
+ }
+}
+
+RVPR2(kabs32, 1, 4);
--
2.17.1
