CMOS doesn't have the notion of reserved spaces, much like E820, so limit the amount of memory above 4G to not acount for the memory above 1Tb.
Suggested-by: David Edmondson <david.edmond...@oracle.com> Signed-off-by: Joao Martins <joao.m.mart...@oracle.com> --- hw/i386/pc.c | 14 ++++++++++++-- include/hw/i386/x86.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 94497f22b908..2e2ea82a4661 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -644,8 +644,12 @@ void pc_cmos_init(PCMachineState *pcms, val = 65535; rtc_set_memory(s, 0x34, val); rtc_set_memory(s, 0x35, val >> 8); - /* memory above 4GiB */ - val = x86ms->above_4g_mem_size / 65536; + /* memory above 4GiB but below 1Tib (where applicable) */ + if (!x86ms->above_1t_mem_size) { + val = x86ms->above_4g_mem_size / 65536; + } else { + val = (x86ms->above_4g_mem_size - x86ms->above_1t_mem_size) / 65536; + } rtc_set_memory(s, 0x5b, val); rtc_set_memory(s, 0x5c, val >> 8); rtc_set_memory(s, 0x5d, val >> 16); @@ -1019,6 +1023,12 @@ void pc_memory_init(PCMachineState *pcms, x86ms->above_4g_mem_size); exit(EXIT_FAILURE); } + + if (nb_iova_ranges != DEFAULT_NR_USABLE_IOVAS) { + x86ms->above_1t_maxram_start = maxram_start; + if (maxram_start > AMD_MAX_PHYSADDR_BELOW_1TB) + x86ms->above_1t_mem_size = maxram_start - 1 * TiB; + } } if (!pcmc->has_reserved_memory && diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 25a1f16f0121..cc22e30bd08c 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -57,6 +57,10 @@ struct X86MachineState { /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; + /* RAM information when there's a hole in 1Tb */ + ram_addr_t above_1t_mem_size; + uint64_t above_1t_maxram_start; + /* CPU and apic information: */ bool apic_xrupt_override; unsigned pci_irq_mask; -- 2.17.1