On 6/17/21 7:43 PM, Philippe Mathieu-Daudé wrote:
> These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
> been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
> More than 11 years later it is safe to assume there won't be added
> soon. The cases fall back to the default which generates a RESERVED
> INSTRUCTION, so it is safe to remove them.
I'll amend for clarity:
"Functionally speaking, the patch is a no-op."
>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
> target/mips/tcg/translate.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index 47c7705f051..5d571d83c54 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -14077,8 +14077,6 @@ enum {
> BGEZALS = 0x13,
> BC2F = 0x14,
> BC2T = 0x15,
> - BPOSGE64 = 0x1a,
> - BPOSGE32 = 0x1b,
> /* These overlap and are distinguished by bit16 of the instruction */
> BC1F = 0x1c,
> BC1T = 0x1d,
> @@ -16122,10 +16120,6 @@ static void decode_micromips32_opc(CPUMIPSState
> *env, DisasContext *ctx)
> generate_exception_err(ctx, EXCP_CpU, 1);
> }
> break;
> - case BPOSGE64:
> - case BPOSGE32:
> - /* MIPS DSP: not implemented */
> - /* Fall through */
> default:
> MIPS_INVAL("pool32i");
> gen_reserved_instruction(ctx);
>
