This patchseries provides an initial slice of the MVE
implementation. (MVE is "vector instructions for M-profile", also
known as Helium).
The series covers:
* framework for MVE decode, including infrastructure for
handling predication, PSR.ECI, etc
* tail-predication forms of low-overhead-loop insns (LCTP, WLSTP, LETP)
* basic (non-gather) loads and stores
* pretty much all the integer 2-operand vector and scalar insns
* most of the integer 1-operand insns
* a handful of other insns
but is not (by a long way) complete MVE support, and this code
will remain 'dead' until the enable-MVE patch eventually lands.
Changes v1->v2:
* Addressed code review comments
* Where some style changes were suggested and made for patches at
the beginning of the series I have retained the r-by tags for
later patches which had minor changes to follow that style:
- adding 'static const' for function pointer arrays
- using mve_check_qreg_bank()
- compressing the early-return-false and early-return-true
checks in trans functions down to fewer lines
- pass only ESIZE, not H, to macros in mve_helper.c
- adjustments to handling of QC
Patches still in need of review are:
04 "target/arm: Add handling for PSR.ECI/ICI"
07 "target/arm: Implement MVE WLSTP insn"
11 "target/arm: Implement MVE VLDR/VSTR (non-widening forms)"
13 "target/arm: Move expand_pred_b() data to translate.c" (new patch)
14 "target/arm: Implement MVE VCLZ"
17 "target/arm: Implement MVE VREV16, VREV32, VREV64"
19 "target/arm: Implement MVE VABS"
21 "tcg: Make gen_dup_i32() public" (new patch)
22 "target/arm: Implement MVE VDUP"
34 "target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH"
35 "target/arm: Implement MVE VADD (scalar)"
45 "target/arm: Implement MVE VQSHL (vector)"
53 "target/arm: Implement MVE VADC, VSBC"
55 "target/arm: Implement MVE VHCADD"
Nobody seemed to object when I posted v1, so I propose to land
these via target-arm.next once they pass code review.
thanks
-- PMM
Peter Maydell (57):
target/arm: Provide and use H8 and H1_8 macros
target/arm: Enable FPSCR.QC bit for MVE
target/arm: Handle VPR semantics in existing code
target/arm: Add handling for PSR.ECI/ICI
target/arm: Let vfp_access_check() handle late NOCP checks
target/arm: Implement MVE LCTP
target/arm: Implement MVE WLSTP insn
target/arm: Implement MVE DLSTP
target/arm: Implement MVE LETP insn
target/arm: Add framework for MVE decode
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
target/arm: Move expand_pred_b() data to translate.c
target/arm: Implement MVE VCLZ
target/arm: Implement MVE VCLS
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
target/arm: Implement MVE VREV16, VREV32, VREV64
target/arm: Implement MVE VMVN (register)
target/arm: Implement MVE VABS
target/arm: Implement MVE VNEG
tcg: Make gen_dup_i32() public
target/arm: Implement MVE VDUP
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
target/arm: Implement MVE VADD, VSUB, VMUL
target/arm: Implement MVE VMULH
target/arm: Implement MVE VRMULH
target/arm: Implement MVE VMAX, VMIN
target/arm: Implement MVE VABD
target/arm: Implement MVE VHADD, VHSUB
target/arm: Implement MVE VMULL
target/arm: Implement MVE VMLALDAV
target/arm: Implement MVE VMLSLDAV
include/qemu/int128.h: Add function to create Int128 from int64_t
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
target/arm: Implement MVE VADD (scalar)
target/arm: Implement MVE VSUB, VMUL (scalar)
target/arm: Implement MVE VHADD, VHSUB (scalar)
target/arm: Implement MVE VBRSR
target/arm: Implement MVE VPST
target/arm: Implement MVE VQADD and VQSUB
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
target/arm: Implement MVE VQDMULL scalar
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
target/arm: Implement MVE VQADD, VQSUB (vector)
target/arm: Implement MVE VQSHL (vector)
target/arm: Implement MVE VQRSHL
target/arm: Implement MVE VSHL insn
target/arm: Implmement MVE VRSHL
target/arm: Implement MVE VQDMLADH and VQRDMLADH
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
target/arm: Implement MVE VQDMULL (vector)
target/arm: Implement MVE VRHADD
target/arm: Implement MVE VADC, VSBC
target/arm: Implement MVE VCADD
target/arm: Implement MVE VHCADD
target/arm: Implement MVE VADDV
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
include/qemu/bitops.h | 29 +
include/qemu/int128.h | 10 +
include/tcg/tcg.h | 3 +
target/arm/helper-mve.h | 357 ++++++++++
target/arm/helper.h | 2 +
target/arm/internals.h | 11 +
target/arm/translate-a32.h | 4 +
target/arm/translate.h | 19 +
target/arm/vec_internal.h | 9 +
target/arm/mve.decode | 260 ++++++++
target/arm/t32.decode | 15 +-
target/arm/m_helper.c | 54 +-
target/arm/mve_helper.c | 1175 +++++++++++++++++++++++++++++++++
target/arm/sve_helper.c | 381 ++++-------
target/arm/translate-m-nocp.c | 16 +-
target/arm/translate-mve.c | 788 ++++++++++++++++++++++
target/arm/translate-vfp.c | 142 +++-
target/arm/translate.c | 300 ++++++++-
target/arm/vec_helper.c | 116 +++-
target/arm/vfp_helper.c | 3 +-
tcg/tcg-op-gvec.c | 4 +-
target/arm/meson.build | 3 +
22 files changed, 3393 insertions(+), 308 deletions(-)
create mode 100644 target/arm/helper-mve.h
create mode 100644 target/arm/mve.decode
create mode 100644 target/arm/mve_helper.c
create mode 100644 target/arm/translate-mve.c
--
2.20.1
