Signed-off-by: Alexey Baturo <space.monkey.deliv...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca..1673872223 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -286,6 +287,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
