On 5/19/21 9:29 AM, Mark Cave-Ayland wrote:
The m68k trace mode is controlled by the top 2 bits in the SR register.
Implement
the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the
CPU
generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each
instruction.
This functionality is used by the NetBSD kernel debugger to allow
single-stepping
on m68k architectures.
Signed-off-by: Mark Cave-Ayland<mark.cave-ayl...@ilande.co.uk>
---
target/m68k/cpu.h | 8 ++++++++
target/m68k/translate.c | 27 ++++++++++++++++++++-------
2 files changed, 28 insertions(+), 7 deletions(-)
It wouldn't be difficult to handle 'trace on change of flow' as well, if you
wanted. But this is certainly good.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
