[Qemu-devel] [PATCH v3 08/16] malta: improve bus implementation of PIIX4 bridge

[Hervé Poussineau]

Signed-off-by: Hervé Poussineau <hpous...@reactos.org>
---
 hw/mips_malta.c |    4 +---
 hw/pc.h         |    2 +-
 hw/piix4.c      |   37 +++++++++++++++++++++++++++++++++++--
 3 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 1ec1228..67e666d 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -943,13 +943,11 @@ void mips_malta_init (ram_addr_t ram_size,
     /* Southbridge */
     ide_drive_get(hd, MAX_IDE_BUS);
 
-    piix4_devfn = piix4_init(pci_bus, 80);
-
     /* Interrupt controller */
     /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
     i8259 = i8259_init(env->irq[2]);
+    piix4_devfn = piix4_init(pci_bus, 80, i8259);
 
-    isa_bus_irqs(i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(9),
diff --git a/hw/pc.h b/hw/pc.h
index 746973f..df7d86a 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -194,7 +194,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int 
*piix_devfn,
 
 /* piix4.c */
 extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, int devfn);
+int piix4_init(PCIBus *bus, int devfn, qemu_irq *isa_irqs);
 
 /* vga.c */
 enum vga_retrace_method {
diff --git a/hw/piix4.c b/hw/piix4.c
index 9addaae..ce11ef4 100644
--- a/hw/piix4.c
+++ b/hw/piix4.c
@@ -27,11 +27,14 @@
 #include "pci.h"
 #include "isa.h"
 #include "sysbus.h"
+#include "exec-memory.h"
 
 PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+    ISABus bus;
+    qemu_irq *isa_irq;
 } PIIX4State;
 
 static void piix4_reset(void *opaque)
@@ -83,21 +86,51 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static qemu_irq pci_piix4_get_irq(ISABus *bus, int isairq)
+{
+    PIIX4State *s = container_of(bus, PIIX4State, bus);
+    if (isairq < 0 || isairq >= 16) {
+        hw_error("isa irq %d invalid", isairq);
+    }
+    return s->isa_irq[isairq];
+}
+
+static MemoryRegion *pci_piix4_get_io_space(ISABus *bus)
+{
+    PIIX4State *s = container_of(bus, PIIX4State, bus);
+    return pci_address_space_io(&s->dev);
+}
+
+static MemoryRegion *pci_piix4_get_memory_space(ISABus *bus)
+{
+    return get_system_memory();
+}
+
+static ISABusOps pci_piix4_ops = {
+    .get_irq = pci_piix4_get_irq,
+    .get_io_space = pci_piix4_get_io_space,
+    .get_memory_space = pci_piix4_get_memory_space,
+};
+
 static int piix4_initfn(PCIDevice *dev)
 {
     PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
 
-    isa_bus_bridge_init(&d->dev.qdev, pci_address_space_io(dev));
+    isa_bus_new(&d->bus, &pci_piix4_ops, &d->dev.qdev);
     piix4_dev = &d->dev;
     qemu_register_reset(piix4_reset, d);
     return 0;
 }
 
-int piix4_init(PCIBus *bus, int devfn)
+int piix4_init(PCIBus *bus, int devfn, qemu_irq *isa_irqs)
 {
     PCIDevice *d;
+    PIIX4State *s;
 
     d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
+    s = DO_UPCAST(PIIX4State, dev, d);
+    s->isa_irq = isa_irqs;
+
     return d->devfn;
 }
 
-- 
1.7.6.3