Tested-by: Ray Wang <xianl...@cn.ibm.com> On 9/26/2011 1:02 PM, Antony Pavlov wrote:
The commit fc2bf44972349b078d8310466c3866615500e67f changed the type of val argument of the function gt64120_writel() from uint32_t to uint64_t, so we need to change the corresponding length modifier from "%x" to "%" PRIx64.Signed-off-by: Antony Pavlov<antonynpav...@gmail.com> --- hw/gt64xxx.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index c7df8c4..1defb6d 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -543,19 +543,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr, /* not really implemented */ s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val& 0xfffffffe)); s->regs[saddr] |= !!(s->regs[saddr]& 0xfffffffe); - DPRINTF("INTRCAUSE %x\n", val); + DPRINTF("INTRCAUSE %" PRIx64 "\n", val); break; case GT_INTRMASK: s->regs[saddr] = val& 0x3c3ffffe; - DPRINTF("INTRMASK %x\n", val); + DPRINTF("INTRMASK %" PRIx64 "\n", val); break; case GT_PCI0_ICMASK: s->regs[saddr] = val& 0x03fffffe; - DPRINTF("ICMASK %x\n", val); + DPRINTF("ICMASK %" PRIx64 "\n", val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] = val& 0x0000003f; - DPRINTF("SERR0MASK %x\n", val); + DPRINTF("SERR0MASK %" PRIx64 "\n", val); break; /* Reserved when only PCI_0 is configured. */
It's good. -- Best Regards, ------------------------------------------------- Ray Wang Linux Technology Center, KVM China IBM Corp., Beijing, China xianl...@cn.ibm.com
