On Tue, 20 Apr 2021 at 13:31, Peter Maydell <peter.mayd...@linaro.org> wrote: > > In tlbi_aa64_vae2is_write() the calculation > bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > pageaddr) > > has the two arms of the ?: expression reversed. Fix the bug. > > Fixes: b6ad6062f1e5 > Reported-by: Rebecca Cran <rebe...@nuviainc.com> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
3 seconds after sending this I realized that the subject isn't right: we flush the correct TLBs, but we might consider the wrong number of bits in the page address to be significant if the TBI enable/disable state is different for SEL2 and NSEL2. Better subject: target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() thanks -- PMM
