On 2021/4/20 上午7:23, Alistair Francis wrote:
On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 11 +++++++++++ target/riscv/csr.c | 26 ++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..1a44ca62c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -159,6 +159,7 @@ struct CPURISCVState { target_ulong mip; uint32_t miclaim; + uint32_t mintstatus; /* clic-spec */ target_ulong mie; target_ulong mideleg; @@ -243,6 +244,7 @@ struct CPURISCVState { /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + void *clic; /* clic interrupt controller */This should be the CLIC type.
OK.Actually there are many versions of CLIC in my branch as different devices. But it is better to use CLIC type for the upstream version.
}; OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..c4ce6ec3d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -165,6 +165,7 @@ #define CSR_MCAUSE 0x342 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +#define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ /* Legacy Machine Trap Handling (priv v1.9.1) */ #define CSR_MBADADDR 0x343 @@ -183,6 +184,7 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +#define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ /* Legacy Supervisor Trap Handling (priv v1.9.1) */ #define CSR_SBADADDR 0x143 @@ -585,6 +587,15 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +/* mintstatus */ +#define MINTSTATUS_MIL 0xff000000 /* mil[7:0] */ +#define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ +#define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ + +/* sintstatus */ +#define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ +#define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */The bit fields in the comments are out of date.
I didn't notice it. Fix it in next version. Thanks. Zhiwei
Alistair+ /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) #define MIE_UEIE (1 << IRQ_U_EXT) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bf..320b18ab60 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); } + +static int clic(CPURISCVState *env, int csrno) +{ + return !!env->clic; +} + #endif /* User Floating-Point CSRs */ @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, return 0; } +static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mintstatus; + return 0; +} + /* Supervisor Trap Setup */ static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, return ret; } +static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + target_ulong mask = SINTSTATUS_SIL | SINTSTATUS_UIL; + *val = env->mintstatus & mask; + return 0; +} + /* Supervisor Protection and Translation */ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, + + /* Machine Mode Core Level Interrupt Controller */ + [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, + + /* Supervisor Mode Core Level Interrupt Controller */ + [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus }, + #endif /* !CONFIG_USER_ONLY */ }; -- 2.25.1
