Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 24 ++++++++++++++++++------
target/riscv/csr.c | 20 ++++++++++++++++----
target/riscv/monitor.c | 22 +++++++++++++++++-----
4 files changed, 51 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index dd643d0f63..6a816ce9c2 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -452,17 +452,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
-#endif
-
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b065ddb681..e5e9339458 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -403,11 +403,21 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP64_MODE);
+ }
} else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
}
widened = 0;
} else {
@@ -622,8 +632,10 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
CPUState *cs = env_cpu(env);
int page_fault_exceptions, vm;
- if (first_stage) {
- vm = get_field(env->satp, SATP_MODE);
+ if (first_stage && riscv_cpu_is_32bit(env)) {
+ vm = get_field(env->satp, SATP32_MODE);
+ } else if (first_stage) {
+ vm = get_field(env->satp, SATP64_MODE);
} else if (riscv_cpu_is_32bit(env)) {
vm = get_field(env->hgatp, SATP32_MODE);
} else {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6052b2d6e9..8abfe33b29 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -927,21 +927,33 @@ static int read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
{
+ int vm, mask, asid;
+
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return 0;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
+ mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+ asid = (val ^ env->satp) & SATP32_ASID;
+ } else {
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
+ mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+ asid = (val ^ env->satp) & SATP64_ASID;
+ }
+
+ if (vm && mask) {
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -RISCV_EXCP_ILLEGAL_INST;
} else {
- if ((val ^ env->satp) & SATP_ASID) {
+ if (asid) {
tlb_flush(env_cpu(env));
}
env->satp = val;
}
}
+
return 0;
}
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index e51188f919..f7e6ea72b3 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
- vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2;
@@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!(env->satp & SATP_MODE)) {
- monitor_printf(mon, "No translation or protection\n");
- return;
+ if (riscv_cpu_is_32bit(env)) {
+ if (!(env->satp & SATP32_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
+ } else {
+ if (!(env->satp & SATP64_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
}
mem_info_svxx(mon, env);
--
2.31.1
