On Fri, Mar 19, 2021 at 3:46 PM Atish Patra <atish.pa...@wdc.com> wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra <atish.pa...@wdc.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/csr.c | 23 +++++++++++++++++++++++
> target/riscv/machine.c | 1 +
> 4 files changed, 30 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7bee351f3c99..ef2a7fdc3980 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -214,6 +214,8 @@ struct CPURISCVState {
> target_ulong scounteren;
> target_ulong mcounteren;
>
> + target_ulong mcountinhibit;
> +
> target_ulong sscratch;
> target_ulong mscratch;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index b42dd4f8d8b1..7514d611cd0b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -283,6 +283,10 @@
> #define CSR_MHPMCOUNTER29 0xb1d
> #define CSR_MHPMCOUNTER30 0xb1e
> #define CSR_MHPMCOUNTER31 0xb1f
> +
> +/* Machine counter-inhibit register */
> +#define CSR_MCOUNTINHIBIT 0x320
> +
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> #define CSR_MHPMEVENT5 0x325
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7166f8d710a8..b9d795389532 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -631,6 +631,26 @@ static int write_mtvec(CPURISCVState *env, int csrno,
> target_ulong val)
> return 0;
> }
>
> +static int read_mcountinhibit(CPURISCVState *env, int csrno, target_ulong
> *val)
> +{
> + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + *val = env->mcountinhibit;
> + return 0;
> +}
> +
> +static int write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong
> val)
> +{
> + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + env->mcountinhibit = val;
> + return 0;
> +}
This will probably need a rebase as a large change to CSR access
functions is in the works.
> +
> static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
> {
> *val = env->mcounteren;
> @@ -1533,6 +1553,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
> [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
>
> + [CSR_MCOUNTINHIBIT] = { "mcountinhibi", any, read_mcountinhibit,
> + write_mcountinhibit },
> +
> [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
> [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 27fcc770aa4b..cb7ec8a4c656 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> VMSTATE_UINT64(env.mfromhost, RISCVCPU),
A bump will be required here.
Otherwise:
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> --
> 2.25.1
>
>
