On 3/19/21 1:35 PM, Peter Maydell wrote: > I'm looking at a bug reported against the QEMU arm virt board's pci-gpex > PCI controller: https://bugs.launchpad.net/qemu/+bug/1918917 > where an attempt to write to an address within the PCI IO window > where the guest hasn't mapped a BAR causes a CPU exception rather than > (what I believe is) the PCI-required behaviour of writes-ignored, reads > return -1. > > What in the QEMU PCI code is responsible for giving the PCI-spec > behaviour for accesses to the PCI IO and memory windows where there > is no BAR? I was expecting the generic PCI code to map a background > memory region over the whole window to do this, but it looks like it > doesn't...
Indeed, this is something I noticed in my generic AddressSpace cleanup series. Currently it is (incorrectly?) done locally by each pci-host implementation, some register the regions behaving as RAZ/WI, some don't.
