On Sun, Feb 28, 2021 at 6:17 AM Asherah Connor <a...@kivikakk.ee> wrote:
>
> Provides fw_cfg for the virt machine on riscv. This enables
> using e.g. ramfb later.
>
> Signed-off-by: Asherah Connor <a...@kivikakk.ee>
This patch doesn't compile, I see this error:
../hw/riscv/virt.c: In function ‘create_fw_cfg’:
../hw/riscv/virt.c:523:27: error: ‘RISCVVirtState’ has no member named ‘fdt’
523 | qemu_fdt_add_subnode(s->fdt, nodename);
| ^~
Can you please fix the compilation failure and send a new version?
Alistair
> ---
>
> Changes in v3:
> * Document why fw_cfg is done when it is.
> * Move VIRT_FW_CFG before VIRT_FLASH.
>
> Changes in v2:
> * Add DMA support (needed for writes).
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
> include/hw/riscv/virt.h | 2 ++
> 3 files changed, 33 insertions(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index facb0cbacc..afaa5e58bb 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -33,6 +33,7 @@ config RISCV_VIRT
> select SIFIVE_PLIC
> select SIFIVE_TEST
> select VIRTIO_MMIO
> + select FW_CFG_DMA
>
> config SIFIVE_E
> bool
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2299b3a6be..82eff42c37 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -56,6 +56,7 @@ static const struct MemmapEntry {
> [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> [VIRT_UART0] = { 0x10000000, 0x100 },
> [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
> + [VIRT_FW_CFG] = { 0x10100000, 0x18 },
> [VIRT_FLASH] = { 0x20000000, 0x4000000 },
> [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
> [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
> @@ -488,6 +489,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
> *sys_mem,
> return dev;
> }
>
> +static FWCfgState *create_fw_cfg(const RISCVVirtState *s)
> +{
> + hwaddr base = virt_memmap[VIRT_FW_CFG].base;
> + hwaddr size = virt_memmap[VIRT_FW_CFG].size;
> + FWCfgState *fw_cfg;
> + char *nodename;
> +
> + fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
> + &address_space_memory);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)MACHINE(s)->smp.cpus);
> +
> + nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
> + qemu_fdt_add_subnode(s->fdt, nodename);
> + qemu_fdt_setprop_string(s->fdt, nodename,
> + "compatible", "qemu,fw-cfg-mmio");
> + qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
> + 2, base, 2, size);
> + qemu_fdt_setprop(s->fdt, nodename, "dma-coherent", NULL, 0);
> + g_free(nodename);
> + return fw_cfg;
> +}
> +
> static void virt_machine_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = virt_memmap;
> @@ -652,6 +675,13 @@ static void virt_machine_init(MachineState *machine)
> start_addr = virt_memmap[VIRT_FLASH].base;
> }
>
> + /*
> + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
> + * tree cannot be altered and we get FDT_ERR_NOSPACE.
> + */
> + s->fw_cfg = create_fw_cfg(s);
> + rom_set_fw(s->fw_cfg);
> +
> /* Compute the fdt load address in dram */
> fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
> machine->ram_size, s->fdt);
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 84b7a3848f..b0ded3fc55 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -40,6 +40,7 @@ struct RISCVVirtState {
> RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
> DeviceState *plic[VIRT_SOCKETS_MAX];
> PFlashCFI01 *flash[2];
> + FWCfgState *fw_cfg;
>
> void *fdt;
> int fdt_size;
> @@ -54,6 +55,7 @@ enum {
> VIRT_PLIC,
> VIRT_UART0,
> VIRT_VIRTIO,
> + VIRT_FW_CFG,
> VIRT_FLASH,
> VIRT_DRAM,
> VIRT_PCIE_MMIO,
> --
> 2.20.1
>
>
