On Wed, Mar 10, 2021 at 5:23 PM Alexander Wagner <alexander.wag...@ulal.de> wrote: > > The IBEX documentation [1] specifies the reset vector to be "the most > significant 3 bytes of the boot address and the reset value (0x80) as > the least significant byte". > > [1] > https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst > > Signed-off-by: Alexander Wagner <alexander.wag...@ulal.de>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > hw/riscv/opentitan.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index e168bffe69..ca4c1be6f6 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState > *dev_soc, Error **errp) > &error_abort); > object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, > &error_abort); > - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, > &error_abort); > + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, > &error_abort); > sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); > > /* Boot ROM */ > -- > 2.25.1 > >
