On 15.09.2011, at 03:24, Benjamin Herrenschmidt wrote: > On Wed, 2011-09-14 at 23:41 +0200, Alexander Graf wrote: >> On 14.09.2011, at 22:42, Richard Henderson wrote: >> >>> On 09/14/2011 01:35 PM, Alexander Graf wrote: >>> >>>>> Can you explain what the memory map looks like from the hardware >> point of view? >>>> >>>> If you can tell me where to find out :). I seriously have zero >> experience in VGA mapping - and it sounds as if Blue has a pretty good >> idea what's going on. >>> >>> He's not interested in the VGA bits, but in the PPC board bits. >>> How are addresses forwarded from the main system bus to the >>> PCI host bridge, for instance? >> >> Yeah, and what I'm trying to tell you is that I know about as much >> about the g3 beige as you do. However, Ben might now a bit more here. >> Let's ask him :). > > Can I have a bit of context please ? :-)
Sure :). So the problem is that when emulating the G3 Beige machine in QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently, on x86 that PCI VGA adapter can map the special VGA regions to somewhere, namely 0xa0000. With the memory api overhaul, this also slipped into the PPC world where mapping 0xa0000 with VGA adapters is a pretty bad idea, as it's occupied by RAM. Now the discussion was on which level that mapping would happen and which devices go through which buses which then would filter certain ranges from being mapped. Basically, which way does a memory request from the CPU go on a G3 Beige machine until it arrives the VGA adapter? I hope that concludes the actual question. Avi, if I explained this wrong, please correct me. Alex
