On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> Translate embedded assembly into IO writes which is more
> readable.
>
> Also hardcode cm_base at boot time instead of reading from CP0.
>
> Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> --
> v3: Use bl_gen_write_ulong.
> ---
> hw/mips/boston.c | 47 ++++++++---------------------------------------
> 1 file changed, 8 insertions(+), 39 deletions(-)
>
> diff --git a/hw/mips/boston.c b/hw/mips/boston.c
> index b976c8199a..06e04ef8de 100644
> --- a/hw/mips/boston.c
> +++ b/hw/mips/boston.c
> @@ -274,48 +274,18 @@ static void boston_register_types(void)
> }
> type_init(boston_register_types)
>
> -static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
> - bool is_64b)
> +static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
> {
> const uint32_t cm_base = 0x16100000;
> const uint32_t gic_base = 0x16120000;
> const uint32_t cpc_base = 0x16200000;
>
> - /* Move CM GCRs */
> - if (is_64b) {
> - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
> - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
> - } else {
> - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
> - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
> - }
> - stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
> - stl_p(p++, 0x01094025); /* or $8, $9 */
> - stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
> - if (is_64b) {
> - stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
> - } else {
> - stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
> - }
> - stl_p(p++, 0x012a4025); /* or $8, $10 */
> -
> - /* Move & enable GIC GCRs */
> - stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
> - stl_p(p++, 0x35290001); /* ori $9, 0x1 */
> - if (is_64b) {
> - stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
> - } else {
> - stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
> - }
> -
> - /* Move & enable CPC GCRs */
If you don't mind I'll keep the comments.
