From: Frank Chang <frank.ch...@sifive.com> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in commit: c445593, but other TB_FLAGS bits for rvv and rvh were not shift as well so these bits may overlap with each other when rvv is enabled.
Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/cpu.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 02758ae0eb4..1b49eb9950b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -379,12 +379,13 @@ typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) -FIELD(TB_FLAGS, LMUL, 3, 2) -FIELD(TB_FLAGS, SEW, 5, 3) -FIELD(TB_FLAGS, VILL, 8, 1) +/* Skip mem_idx bits */ +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) +FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, SEW, 6, 3) +FIELD(TB_FLAGS, VILL, 9, 1) /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, HLSX, 10, 1) bool riscv_cpu_is_32bit(CPURISCVState *env); -- 2.17.1
