On Mon, Jan 25, 2021 at 11:34 PM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > On 1/26/21 7:00 AM, Bin Meng wrote: > > From: Bin Meng <bin.m...@windriver.com> > > > > This adds the SiFive SPI controller model for the FU540 SoC. > > The direct memory-mapped SPI flash mode is unsupported. > > > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > > > > --- > > > > Changes in v3: > > - Simplify flush txfifo logic > > > > Changes in v2: > > - Log guest error when trying to write reserved registers > > - Log guest error when trying to access out-of-bounds registers > > - log guest error when writing to reserved bits for chip select > > registers and watermark registers > > - Log unimplemented warning when trying to write direct-map flash > > interface registers > > - Add test tx fifo full logic in sifive_spi_read(), hence remove > > setting the tx fifo full flag in sifive_spi_write(). > > - Populate register with their default value > > > > include/hw/ssi/sifive_spi.h | 47 +++++ > > hw/ssi/sifive_spi.c | 358 ++++++++++++++++++++++++++++++++++++ > > hw/ssi/Kconfig | 4 + > > hw/ssi/meson.build | 1 + > > 4 files changed, 410 insertions(+) > > create mode 100644 include/hw/ssi/sifive_spi.h > > create mode 100644 hw/ssi/sifive_spi.c > > Missing MAINTAINERS entry (if there are no other comments on > this series, maybe the maintainer can directly add one).
Yep, I'm adding this section to the RISC-V machines: diff --git a/MAINTAINERS b/MAINTAINERS index 8d8b0bf966..c347d49bd2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h F: include/hw/misc/mchp_pfsoc_ioscb.h F: include/hw/misc/mchp_pfsoc_sysreg.h +SiFive Machines +M: Alistair Francis <alistair.fran...@wdc.com> +M: Bin Meng <bin.m...@windriver.com> +M: Palmer Dabbelt <pal...@dabbelt.com> +L: qemu-ri...@nongnu.org +S: Supported +F: hw/*/*sifive*.c +F: include/hw/*/*sifive*.h + RX Machines ----------- rx-gdbsim Can I get an Ack from you Bin that you are ok with that? @Palmer Dabbelt let me know if you would prefer something else. Alistair >
